This application is based on and claims the benefit of German Patent Application No. 198 17 024.6, which is incorporated by reference herein.
The invention concerns an integrated circuit according to the characterizing portion of claim 1. An integrated circuit of this type serves in particular to process data, for example, filtering, transformation, and/or modulation of data.
An arrangement known from Proceedings of the 5th International Conference on Signal Processing Applications and Technology, Volume 1, 1994 pages 85-90, provides for the use of a digital signal processor for various language coding applications as the core of an ASIC. The digital signal processor is used among other things for routine applications which could also be performed by separate modules that function exclusively according to special operating regulations that differ from each other, the modules being able to execute the special routine tasks more efficiently than the digital signal processor. As a result of the routine applications, approximately 25% of the computing capacity is occupied in the digital signal processor. But even if the routine tasks were all performed in separate modules, the task of controlling the data transfer from and to the modules must still be handled by the signal processor which would further impair its computing capacity. For example, the digital signal processor often serves only as a relay station if, for example, several modules must be run sequentially but the data packets must be sent with central coordination from digital signal processor to module 1, received by module 1, sent to module 2, received by module 2, sent to module 3, etc. The computing capacity of the digital signal processor is needed in ASICs primarily for special, customer oriented applications.
It is, therefore, an object of the invention to optimize the exploitation of the computing capacity of a processor of an integrated circuit.
This object is achieved a through an integrated circuit according to claim 1. This integrated circuit is characterized in particular in that it contains a router which controls the data traffic between the processor and the modules. Through the use of the router, the triggering of the modules is removed from the processor. Computing time is therefore saved for the processor which can be used for more primary tasks. The router is connected between the processor and the modules and in this manner can direct data packets to several modules sequentially without blocking computing time of the processor. The router accepts orders of the processor and delivers results of the executed orders to processor. By way of example, an order can be: The following data packet should be sequentially transformed, modulated, and filtered. The router is connected to three modules. Each module fulfills a special task. Thus data packets can be filtered in module 1, for example, modulated in module 2, and transformed in module 3. The router receives the data packet which is to be processed from the processor and directs it independently to the modules 3, 2, 1 sequentially. At this point, the data packet has been processed according to the order and is directed to the processor. In this manner, the processor is saved the time for the execution of the order and can use the saved time for other tasks which are not so trivial.
In a preferred exemplary embodiment, processor and router are constructed such that data packets and associated instructions for special operations that can be performed by the modules to be performed for individual data packets in the specified sequence are transferred by the processor to the router. The router assumes the control of the sequence autonomously. It coordinates the transport of data packets from and to the proper modules. If the data packets are to be processed following the specified instructions, it transfers them to the processor. The processor thus assumes the role of the order giver which issues an instruction for each data packet and transfers them to the router. The router is the order receiver which transfers the data packets processed in accordance to the instruction to the appropriate modules. The number of modules is limited, with result that the number of instructions is also limited. It is therefore possible to realize the router in a simple manner, for example as an allocation table. Four modules can be addressed with 2 bits, for example module 1 by 01, module 2 by 10, and module 3 by 11. An instruction in bits, for example, would be 011011. The first 2 bits mean that the data packet should first be directed to module 1. The third and fourth bits mean that the data packet should be directed to module 2 after module 1. The fifth and sixth bits mean that the data packet should be directed to module 3 after module 2. Thus, in instruction 110110, modules 3, 1, 2 should be passed through sequentially.
In another preferred exemplary embodiment, the integrated circuit contains a memory for temporary storage of data packets to be processed. The router is connected to the memory. The router receives from the processor, for example, several data packets simultaneously with associated instructions. It is quite possible that different data packets will pass through different modules and in the process a temporary overlapping of the access to the same module might occur. In order to exclude the possibility that a module which is already processing a data packet will receive from the router an additional data packet to process, which would result in a conflict, memory is provided. The router knows which data packet it sent to which module and from which module it has already received the appropriately processed data packet. It coordinates the transfer of data packets independently and is responsible for ensuring that no conflicts occur. If the module is already processing the data packet, the router temporarily stores in the memory an additional data packet to be processed in this module. The additional data packet will only be transferred to the module when it is available. The computing capacity of modules also is optimally used in this manner.
In a further preferred embodiment, the router contains a control unit which has an interface to the processor. Through this interface, data packets and instructions are transferred from the processor to the control unit and processed data packets are transferred from the control unit to the processor. The control unit separates the received data packets from the received instructions. The instructions are evaluated in the control unit, for example, by means of the above described allocation table and then under the control of the control unit, the separated data packets are transferred in the appropriate sequence to the appropriate modules, if appropriate with time delay as a result of a temporary storage in the memory. The instructions are transferred, for example, in a so-called header to the individual data packets. By way of example, each header contains synchronizing bits. This simplifies communication between processor and control unit.
In a further preferred embodiment, the router contains several switches. All switches are triggered by the control unit. The switches are arranged and connected in such a manner that data packets from each module can be forwarded to each other module by means of the switches. The control unit separates the received data packets from the received instructions, evaluates the instructions, and transfers the separated data packets in accordance with the associated instructions to the appropriate modules through appropriately triggering the switches. Through the use of the switches, a flexible and easily modified connection means is provided with the modules and among the modules by which means the instructions can be implemented in a simple manner. The switches are standard components, such as 2xc3x972 switches, which require little chip space. The number of switches is matched to the number of modules. In the case of four modules and one memory, for example, only eight 2xc3x972 switches are required.
In a further preferred embodiment, the control unit transfers the processed data packets together with additional information containing an identifier of the processed data packet through the interface to the processor. A header can also be used for the transfer. In this manner, the same format, header plus associated data packet, can be used in both directions, from the processor to the control unit and from the control unit to the processor. The header contains synchronization bits for both directions: for the direction to the control unit, additional instructions and for the direction to the processor, identifiers. This simplifies communication between processor and control unit.